With recent improvements in performances of electronic devices, there have been adopted configurations where several types of MOS transistors different in operating voltage and operating speed are mounted on a single semiconductor substrate.
A MOS transistor includes impurity regions such as a channel region, source and drain regions, extension regions, and pocket regions. Among them, the channel region is an impurity region provided in the semiconductor substrate between the source and drain regions. An impurity concentration of the channel region relates to a threshold voltage of the MOS transistor.
The extension regions are impurity regions provided between the channel region and the source and drain regions, respectively, and are formed to have a lower impurity concentration than the source and drain regions. The extension regions may prevent concentration of a high electric field between the channel region and the source and drain regions and suppress generation of hot carriers.
Further, the pocket regions are impurity regions formed by doping an impurity into the semiconductor substrate below a gate electrode, the impurity having an opposite conductivity type to the conductivity type of the source and drain regions. The pocket regions are provided to suppress a short channel effect between the source and drain regions.
These impurity regions are individually formed by implanting ions of the impurities into the semiconductor substrate. However, in a product in which several types of MOS transistors are mounted as described above, such a configuration leads to an increase in the number of ion implantation processes and thereby to an increase in manufacturing costs.    Patent Document 1: Japanese Laid-open Patent Publication No. 2000-68389